The invention is directed to an improved approach for implementing inherited connections for electronic designs.
Modern electronic design activities are typically performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language (HDL). Common examples of HDLs include Verilog and VHDL. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction. Essentially, the process to implement an electronic device begins with functional design and verification (e.g., using RTL), and then proceeds to physical design and verification.
Many modern electronic designs, such as a typical semiconductor integrated circuit (IC) design, are complex designs that include a large number of electronic components such as transistors, logic gates, and diodes. These complex designs are often implemented hierarchically with circuit schematics that are also hierarchical in nature.
Each portion (e.g., block or cell) of the hierarchical design may correspond to multiple levels of ancestor or descendent portions that may relate to inherited relationships for certain design or electronic properties. For example, consider the connections that need to be established between nets and/or pins in an electronic design. These connections may be explicitly specified by a designer. However, for many complex designs having a significantly large number of pins and nets, it is often impractical for a designer to individually specify a connection for each and every pin and net. Therefore, EDA tools can be implemented to automatically provide these connections using the concept of “inherited connections,” in which a connection is established for an electronic component based upon the connection properties that are inherited from a related portion of the design somewhere in the design hierarchy. For example, inherited connections may be specified via a rule-based scheme, such that the hierarchy of a design is searched using the rule to identify whether or not an ancestor component specifies a connection that should be inherited by the child component. If the rule-based search successfully identifies a specified connection that can be inherited, then the inherited connections approach can be successfully used to implement the connections.
A possible problem with this approach arises when the rules-based search fails to identify an appropriate connection that can be inherited for the component. In this situation, it is possible that a “default” connection or default global net (such as VDD for power connections) is utilized as the connection upon such a failure to identify an inherited connection. This may not be a significant problem if the entire design is implemented by a single designer or by a small group of integrated designers, since they would all collectively have the same understanding as far as which connection should be utilized by default in this situation.
However, many (if not most) modern complex designs are not (and often cannot) be wholly implemented using a single designer or a small group of integrated designers. Instead, modern electronic designs are often implemented using components that are acquired from external IP (intellectual property) sources, whether within the same company or from third party vendors. In this situation, assigning a default global net connection upon failure to find a suitable inherited connection could present a serious problem. This is because two items of IP that did not explicitly specific a connection or an inherited connection may both end up connecting to the same global net by default, and the default connection to the default global net may therefore inadvertently create a short circuit between the two components that could cause operational problems for the circuit design.
Therefore, there is a need for an improved approach for implementing inherited connections for electronic designs that avoids the problems with prior approaches.